1. Field of the Invention
The present invention relates to a solid-state imaging device including a plurality of vertical charge transferring portions and a horizontal charge transferring portion connected to one end or both ends of the vertical charge transferring portions, and a method for producing the same.
2. Description of the Related Art
An interline-transfer solid-state imaging device includes a plurality of photoelectric exchanging portions arranged in a matrix, a plurality of arrays of vertical charge transferring portions arranged corresponding to each array of the photoelectric exchanging portions, a horizontal charge transferring portion electrically connected to one end of each vertical charge transferring portion, and an output circuit portion connected to one end of the horizontal charge transferring portion. In such a solid-state imaging device, signal charges generated in the photoelectric exchanging portions are transferred in the vertical direction by the vertical charge transferring portions and then to the horizontal charge transferring portion. In the horizontal transferring portion, the signal charges are transferred in the horizontal direction (direction orthogonal to the transfer direction of the vertical charge transferring portions) to the output circuit portion.
The conventional structure of the connection portion between the vertical charge transferring portions and the horizontal charge transferring portion of such a solid-state imaging device is described, for example, in JP 5-29599A and JP 10-135439 A. FIGS. 19A and 19B are schematic views showing the structure in the vicinity of the connection portion between the vertical charge transferring portions and the horizontal charge transferring portion of the conventional interline-transfer solid-state imaging device. FIG. 19A is a plan view and FIG. 19B is a cross-sectional view taken along line A-A′ of the FIG. 19A.
In the vertical charge transferring portion 501, a vertical p-type well 503 is formed in a surface layer portion of an n−−-type semiconductor substrate 502, and an n-type vertical transfer channel 504 is formed in the surface layer portion of the vertical p-type well 503. A plurality of vertical transfer electrodes 507, 509a, and 509b and a final vertical transfer electrode 508 are formed on the surface of the n−−-type semiconductor substrate 502 via a gate insulating film 506. The vertical transfer electrodes are wired such that a clock pulse φV1, φV2, φV3, or φV4 is applied to the vertical transfer electrodes. In the vertical charge transferring portion 501, a p+-type element separating region 505 for electrically separating between the vertical transfer channels 504 is formed.
In the horizontal charge transferring portion 510, a horizontal p-type well 511 is formed in a surface layer portion of the n−−-type semiconductor substrate 502, and an n-type horizontal transfer channel 512 is formed in the surface layer portion of the horizontal p-type well 511. A plurality of first horizontal transfer electrodes 513a and 513b are formed on the surface of the n−−-type semiconductor substrate 502 via the gate insulating film 506. Furthermore, an n−-type potential barrier region 514 is formed in a gap between the first horizontal transfer electrodes and a gap between the final vertical transfer electrode 508 and the first horizontal transfer electrode 513a, and second horizontal transfer electrodes 515a and 515b are formed on the potential barrier region 514 via the gate insulating film 506. The horizontal transfer electrodes are wired such that a clock pulse φH1 or φH2 is applied to the horizontal transfer electrodes.
In the connection portion between the vertical charge transferring portion 501 and horizontal charge transferring portion 510, the p+-type element separating region 505 extends from the side of the vertical charge transferring portion 501. In this connection portion, the horizontal transfer channel 512 extends from the horizontal charge transferring portion 510 side. The portion of the horizontal transfer channel 512 that extends in the connection portion is placed between the p+-type element separating regions 505. On the other hand, the vertical transfer channel 504 does not extend in the connection portion, and the end portion 521 thereof on the side of the horizontal charge transferring portion substantially matches the end portion of the final vertical transfer electrode 508. In this connection portion, the n−-type potential barrier region 514 is formed on a portion corresponding to the boundary between the vertical transfer channel 504 and the horizontal transfer channel 512.
The channel width of the vertical transfer channel 504 is narrower than that of the horizontal transfer channel 512, and therefore the impurity concentration of the vertical transfer channel 504 is higher than that of the horizontal transfer channel 512 in order to ensure the amount of transfer signals. Since the horizontal charge transferring portion 510 has a higher transfer frequency than that of the vertical charge transferring portion 501, the p-type impurity concentration of the horizontal p-type well 511 is lower than that of the vertical p-type well 503 so as to intensify the transfer electric field.
Next, the charge transfer operation from the vertical charge transferring portion to the horizontal charge transferring portion will be described with reference to FIGS. 20 and 21. FIG. 21 shows an example of clock pulses that are applied to the electrodes of the vertical charge transferring portions and the horizontal charge transferring portion. FIG. 20 is a diagram showing a potential distribution during charge transfer from the vertical charge transferring portion to the horizontal charge transferring portion when they are driven by the clock pulses shown in FIG. 21. In the potential diagram, it is assumed that the downward potential is positive and charges are held in a hatched portion (which also applies to the following).
At a time t1, the signal charge 517 in the vertical charge transferring portion 501 is accumulated below the first vertical transfer electrode 507 and the second vertical transfer electrode 509b to which a high voltage VVH is applied. Next, at a time t2, the clock pulse φV4 changes from VVL to VVH, and the clock pulse φV2 changes from VVH to VVL, so that a part of the signal charge 517 is started to be transferred from the vertical charge transferring portion 501 to the horizontal charge transferring portion 510. Then, at a time t3, the dock pulse φV1 changes from VVL to VVH, and the dock pulse φV3 changes from VVH to VVL, so that the signal charge 517 further is transferred from the vertical charge transferring portion 501 to the horizontal charge transferring portion 510. At a time t4, the clock pulse φV2 changes from VVL to VVH, and the clock pulse φV4 changes from VVH to VVL, and thus the operation of the transfer of the signal charge 517 from the vertical charge transferring portion 501 to the horizontal charge transferring portion 510 is completed. At this point, the signal charge 517 is accumulated in the first horizontal transfer electrode 513a to which VHH of the horizontal charge transferring portion 510 is applied. Furthermore, the next signal charge 518 has been transferred up to a portion below the first vertical transfer electrode 507 and the second vertical transfer electrode 509a to which a high voltage VVH is applied. At a time t5, the clock pulse φV3 changes from VVL to VVH, and the clock pulse φV1 changes from VVH to VVL, so that the next signal charge 518 is transferred up to a portion below the first vertical transfer electrode 507 and the second vertical transfer electrode 509b to which a high voltage VVH is applied. Thereafter, the horizontal charge transferring portion 510 is operated so that transfer pulses φH1 and φH2 that have opposite phases to each other are applied to the horizontal transfer electrodes, and the signal charge 517 is transferred in the horizontal charge transferring portion. Thereafter, by repeating this operation, the signal charge 517 is transferred in the vertical charge transferring portion 501 and the horizontal charge transferring portion 510.
As shown in FIG. 20, in the connection portion between the vertical charge transferring portion and the horizontal charge transferring portion, a potential barrier 519 is present because of the potential barrier region 514 formed below the second horizontal transfer electrode 515a, and further a potential barrier 520 is present as a result of a narrow channel effect caused by the element isolating region 505 of the vertical charge transferring portion. Therefore, the reverse transfer of the signal charge from the horizontal charge transferring portion to the vertical charge transferring portion is prevented.
Next, a method for producing the solid-state imaging device will be described. FIGS. 22A, 22B, 23A, 23B, 24A, 24B, 25A and 25B are views for illustrating a method for producing the solid-state imaging device. FIGS. 22A, 23A, 24A and 25A show portions corresponding to the cross sections taken along line A-A′ of FIG. 19A, and FIGS. 22B, 23B, 24B and 25B show portions corresponding to the cross sections taken along line B-B′ of FIG. 19A.
First, as shown in FIGS. 22A and 22B, a protective film 526 is formed on the surface of the n−−-type semiconductor substrate 502, and the element isolating region 505 is formed by implanting ions of p-type impurities such as boron in a region other than the regions in which a vertical transfer channel and a horizontal transfer channel are to be formed in the surface layer portion of the n−−-type semiconductor substrate 502. Then, a first photoresist film 534 is formed on the surface of the protective film 526, and the first photoresist film 534 is removed from the regions in which a vertical transfer channel and a horizontal transfer channel are to be formed, and then a p-type region 524 is formed by implanting ions of p-type impurities such as boron in the surface layer portion of the n−−-type semiconductor substrate 502. An n-type region 525 is formed by implanting ions of n-type impurities such as phosphorus or arsenic in the surface layer portion of the p-type region 524.
Then, after the first photoresist film 534 is removed entirely, as shown in FIGS. 23A and 23B, a second photoresist film 528 is formed on the surface of the protective film, and the second photoresist film 528 is removed from the region in which a vertical transfer channel is to be formed, and then a vertical p-type well 503 is formed by implanting ions of p-type impurities such as boron in substantially the same depth as the p-type region 524, and a vertical transfer channel 504 is formed by implanting ions of n-type impurities such as phosphorus or arsenic in substantially the same depth as the n-type region 525. Here, the portions of the p-type region 524 and the n-type region 525 in which the vertical p-type well 503 and the vertical transfer channel 504 are not formed serve as the horizontal p-type well 511 and the horizontal transfer channel 512, respectively.
Then, after the second photoresist film 528 and the protective film 526 are removed entirely, as shown in FIGS. 24A and 24B, the gate insulating film 506 is formed, and transfer electrodes 507, 508, 513a and 513b of the first layer are formed on the gate insulating film 506. Then, a third photoresist film 529 is formed on the surface thereof. After this film is removed from the region on the side of the horizontal transfer channel such that the boundary is on the final vertical transfer electrode 508, the n−-type potential barrier region 514 is formed by implanting ions of p-type impurities such as boron.
Then, after the third photoresist film 529 is removed entirely, as shown in FIGS. 25A and 25B, an interlayer insulating film 527 is formed around the transfer electrodes 507, 508, 513a and 513b of the first layer, and then transfer electrodes 509a, 509b, 515a and 515b of the second layer are formed. Wiring is performed by metal films such as aluminum or tungsten such that clock pluses φV1, φV2, φV3, and φV4 can be applied to the vertical transfer electrode 509a, 507, 509b and 508, and that clock pluses φH and φH2 can be applied to a pair of horizontal transfer electrodes 513a and 515a, and a pair of horizontal transfer electrodes 513b and 515b. Thus, the conventional solid-state imaging device can be produced.
However, in the conventional solid-state imaging device, the charge transfer from the vertical charge transferring portion to the horizontal charge transferring portion cannot be performed smoothly in a sufficiently short time as the miniaturization of pixels, the high-speed driving of the vertical charge transferring portion and the low voltage driving of the horizontal charge transferring portion are promoted, and abnormal display such as appearance of vertical lines generally called black line defects occurs, or the transfer efficiency is deteriorated significantly. The reasons why these problems occur will be described with reference to FIG. 20.
In the conventional solid-state imaging device, with the miniaturization of pixels, the channel width of the vertical transfer channel 504 should be decreased, so that it is necessary to increase the n-type impurity concentration of the vertical transfer channel 504 in order to ensure the amount of transfer charges. On the other hand, it is not necessary to decrease the channel width of the horizontal transfer channel 512, so that it is not necessary to increase the n-type impurity concentration of the horizontal transfer channel 512.
Furthermore, in the conventional solid-state imaging device, the end portion 521 of the vertical transfer channel 504 on the side of the horizontal charge transferring portion is formed so as to substantially match the end portion of the final vertical transfer electrode 508, and the potential barrier region 514 and the horizontal transfer channel 512 are formed more on the side of the horizontal charge transferring portion than the end portion of the final vertical transfer electrode 508. In other words, the vertical transfer channel 504 having a high n-type impurity concentration is formed below the final vertical transfer electrode 508, and the horizontal transfer channel 512 having a low n-type impurity concentration is formed in a region below the first horizontal transfer electrode 513a and the second horizontal transfer electrode 515a in the connection portion between the vertical charge transferring portion 501 and the horizontal charge transferring portion 510.
Therefore, when the n-type impurity concentration difference between the vertical transfer channel 504 and the horizontal transfer channel 512 is increased or the low voltage driving of the horizontal charge transferring portion is promoted, the channel potential below the second horizontal transfer electrode 515a and the first horizontal transfer electrode 513a (to which VHH is applied) in the connection portion is formed in a smaller depth than the channel potential below the final vertical transfer electrode 508 (to which VVH is applied). Thus, the transfer barrier 523 is formed at times t2 and t3 in FIG. 20. As a result, all the signal charges 517a and 517b left in the vertical charge transferring portion 501 cannot be transferred to the horizontal charge transferring portion 510 in a short time from a time t4 to a time of the start of operation of the horizontal charge transferring portion, and untransferred signal charges 522 are generated and abnormal display such as the appearance of vertical lines called black line defects may occur.
In order not to generate the transfer barrier 523 as described above, the final vertical transfer electrode 508 is formed independently of other vertical transfer electrodes to which φV4 is applied, and a clock pulse φV4′ with a lower voltage than the high level voltage VVH can be applied to the final vertical transfer electrode 508. In this case, however, poor transfer occurs anew from the second vertical transfer electrode 509b to the final vertical transfer electrode 508, and a separate power source for generating the clock pulse φV4′ is required so that a driving circuit becomes complicated.
In the method for producing the conventional solid-state imaging device as described above, with the miniaturization of pixels, a variation in the amount of transfer charge in the vertical charge transferring portion is increased because of displacement of mask alignment. The reason why this problem occurs will be described with reference to FIG. 22.
The vertical transfer channel 504 and the vertical p-type well 503 are formed, as described above, by implanting ions of n-type impurities and p-type impurities after the first photoresist film 534 is patterned and removed [FIGS. 22A and 22B], then by implanting ions of n-type impurities and p-type impurities after the second photoresist film 528 is patterned and removed [FIGS. 23A and 23B]. Thus, the vertical transfer channel 504 and the vertical p-type well 503 are formed in two photoresist processes, so that the displacement of the mask alignment between the first photoresist process and the second photoresist process may cause variation in the width of the vertical transfer channel 504 or the vertical p-type well 503 to be formed. As a result, in particular, as the size of the pixels is decreased, a variation in the amount of transfer charge in the vertical charge transferring portion is increased.